1. Technical Field
The present invention relates to a bit-line sense amplifier driver, in particular, to a bit-line sense amplifier driver which overdrives a sense amplifier in a high speed operation memory device in a refresh mode.
2. Related Art
The data processing speed of graphics memory devices such as GDDR4 and next-generation general purpose memory devices such as DDR2 or DDR3 are being improved, which is attributable to higher operational frequencies. Therefore, stabilizing operation voltages in a high speed operation is becoming an issue. Further, the above memory devices are susceptible to noises caused by the operating power supply such that the operational characteristics are determined by the noise in the power supply. Accordingly, stabilizing the internal power supply is becoming more important.
In order to drive a sense amplifier which activates bit-line and bit-line bar nodes, memory devices generally use an overdriving method that abruptly applies an external supply voltage VDD to a sense amplifier driver which uses an internal supply voltage VCORE of the memory device in an active mode.
FIGS. 1 and 2 are views showing a bit-line sense amplifier used generally.
When a bit-line equalizing signal BLEQ is at a high level, N-type-transistors 102, 104, 106 are turned on and a voltage between a sense amplifier power line, i.e. RTO signal input line and a sense amplifier ground line, i.e. SB signal input line serves as a first voltage VBLP. Thereafter, when an active command is enabled to make the BLEQ signal reach a low level, and a word line selection signal is enabled, charge sharing is commenced in a bit-line pair, e.g. BL and BLb.
Bit-line sensing refers to sensing the amount of charge shared in the bit-line pair of a memory cell. For that purpose, the voltage applied to the bit-line pair BL and BLb must be amplified. Therefore, in order to activate enable signals SAP and SAN of the bit-line sense amplifier driver, a first enable signal SAP is pulled low, and a second enable signal SAN is pulled high.
Accordingly, a P-type transistor 108 and an N-type transistor 110 are individually turned on so that a voltage level of the sense amplifier power line shifts from the first voltage VBLP to a second voltage of the internal supply voltage VCORE. Furthermore, a voltage applied to the sense amplifier ground line SB shifts from a first voltage to a ground voltage VSS.
Voltages applied to the sense amplifier power line RTO and the sense amplifier ground line SB serve as a power source of the sense amplifier to sense the amount of charge by amplifying the voltage level of the bit-line pair BL and BLb which start to perform the charge sharing. In this case, when the difference between the voltage levels of the bit-line pair BL and BLb exceeds a predetermined value, the charge sensing is performed accurately. Therefore, by enabling an overdriving control signal OVD, the external supply voltage VDD is applied to the sense amplifier power line via a P-type transistor 100 or 200.
In this case, the P-type transistor 100 or 200 which is driven by the overdriving control signal OVD may be coupled to the terminal of the external power supply voltage VDD and the terminal of the sense amplifier power line output voltage RTO (see FIG. 1) or between the terminal of the external power supply voltage VDD and the terminal of the internal power supply voltage VCORE (see FIG. 2).
In a high speed operation memory device, however, it is important to maintain a stable supply voltage. A problem of the above method is that the performance of the memory device is adversely affected because the driving supply voltage serves as noise during overdriving. The stable operation of the memory device is further hindered due to rising of the internal supply voltage VCORE caused by overdriving. That is to say, the external power supply VDD is abruptly consumed in the memory device during the overdriving, which causes the potential of the external power supply VDD to become unstable due to a large application current. Accordingly, the unstable external power supply VDD may result in malfunction or operational error of the memory device that is sensitive to the driving voltage fluctuation.
A length of a column address of the high speed operation memory device is not significant, and due to the development of elements and processing technology, the overdriving operation is not required because, in a normal mode where banks are independently activated, the operation speed is not adversely affected even when the overdriving is not performed. But, in the refresh mode, all banks of the memory device must be activated, which weakens the internal power supply voltage. Therefore, in the refresh mode, the overdriving must be performed to ensure satisfactory restoration of the memory cells.